In integrated circuits, signals are often transmitted on signal lines for relatively long distances across the IC. The resulting resistance and capacitive loading introduces delay to the signal. For some heavily loaded signal lines, the delay is crucial to the function of the circuit. Therefore, such lines are often buffered, i.e., driver circuits are provided that accept an input signal at an input terminal and mirror the input signal as an output signal on an output terminal, with increased drive capability. Available driver circuits, however, impose a delay between the input and output signals that must be taken into account when designing ICs. Therefore, while the overall path delay can be reduced by using a driver circuit, the path delay cannot be reduced beyond the delay through the driver circuit.
In field programmable gate arrays (FPGAS), general interconnect lines are provided that can be programmed to be used for many different functions. (One such FPGA, the Xilinx XC4000.TM. Series FPGA, is described in detail in pages 4-5 through 4-69 of the Xilinx 1998 Data Book entitled "The Programmable Logic Data Book 1998" (hereinafter referred to as "the Xilinx Data Book"), published in 1998 and available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference. Xilinx, Inc., owner of the copyright, has no objection to copying these and other pages referenced herein but otherwise reserves all copyright rights whatsoever.) The signals on these general interconnect lines may have a high or low fanout, and may be of greater or lesser importance in determining the operating frequency of the design. Therefore, the need for buffering on such lines is difficult to predict. As a consequence, the longer general interconnect lines are usually buffered at all times in order to accommodate the worse case scenario. A signal traversing a large number of these buffers (i.e., a signal routed on a succession of programmably coupled general interconnect lines) incurs more delay than a signal traversing a smaller number of buffers. Therefore, the two signals are "skewed" relative to one another. This skew considerably complicates the task of implementing time-critical circuits in FPGAs.
Therefore, it is desirable to provide a buffer having a zero delay, so that a difference in the number of buffers traversed does not introduce skew between two signals. It is further desirable to provide an IC driver circuit having a negative delay, to compensate for delays in logic circuits on a signal path. It is yet further desirable to provide an IC driver circuit having an adjustable delay, so that delays in different paths can be adjusted to minimize skew.
It is also desirable to provide an IC driver circuit having a low noise sensitivity, and further to provide an IC driver circuit that it is programmably either high-speed (low delay) or noise-insensitive.